Hi All,

A SAR would be interesting, especially if you add a multiplexer for the clock!
So clock should be selectable between programmable frequency divider from internal clock and
also to be set to external clock. External clock is important if one has noise generated by switch mode power supply
or just AC (50Hz/60Hz). External clock allows to synchronize the sampling clock with the noise and thus helps to
eliminate the noise from the samples because of the averaging effect of SAR.
May be we are able to have a PLL with a programmable frequency divider to generate higher
Sampling frequencies that can be synchronized with external clock.
If not, we would require an external PLL.

Cheers,

Ludwig


On Thu, Jan 3, 2019 at 1:22 AM Éger Ferenc <eegerferenc@gmail.com> wrote:
Hello Everyone,

Congratulations for the 35C3 presentation. I could not be there personally, but I checked it out online. For the ADC topic, I would suggest to start with a 10 to 12 bit SAR, built around a R-2R or divide-add DAC at first. The SAR is fairly common in general-purpose MCUs, and these architectures are both need no special features (pure MOS design) and can be designed relatively easily (both DACs are a series of identical cells, allowing for a bottom-up design).

Regards,
Ferenc


On Wed, Jan 2, 2019 at 2:30 PM Christoph Maier <cm.hardware.software.elsewhere@gmail.com> wrote:
Hi Tim,

On Wed, Jan 2, 2019 at 2:15 PM Tim Edwards <tim@opencircuitdesign.com> wrote:
>
> Hello Christoph a.k.a. Tatzelbrumm:
>
> > Setting up lines of communication <mumble mumble>
> > and refreshing memories <Hasler [Pronouns: she, her], Diorio,
> > Minch>(remember those, Mr. Potbox?) <SONOS>
> > in order to get involved and productive.
>
> I have not been in contact with Jen Hasler since the early 2000s, but I
> have been in touch with one of her associates previously at Georgia
> Tech, Brian "Degs" Degnan, who was involved in the first customer
> taped-out design from efabless (currently in fab).  Chris Diorio, I
> have not heard from since the late 1990s.  Brad Minch still occasionally
> exchanges emails with me about various EDA tool issues.

I was just thinking about some non-standard analog structures one
might try out on the Pearl River process (speaking of, I had some
AFGAs on AMS CXE or some such and tested/fried them when visiting
newly established assistant professor PAUL Hasler at Georgia Tech in
2000).

> If it's possible to design an ADC in the Libre-Silicon process, then
> maybe it's time to start discussing onboarding the process on the
> efabless design platform.
First things first: What are appropriate test structures (like,
transistor, resistor, and capacitor arrays)
that allow us to characterize devices AND device matching in a way to
allow meaningful analog/mixed signal design?
I would assume that you already have put quite a bit of thought into
this, if and when a really open silicon process ever became available
(like, now, with these crazy guys here).
I'm not sure yet (and open to whatever suggestions I could get from
People Skilled In The Art) what ADC topologies would be suitable to
try out.

IIRC, efabless has venture capital, so what are the strings (i.e.,
exclusive representation rights or some such) attached to importing
designs and PDKs into your infrastructure?

For now, I just established mumble communication with Hagen and
Leviathan, and next I'm planning to dig into the gds, and how to use
the magic et al. tool suite. I'll pester you with questions about your
tools to the extent you'll let me.

TTYL soon
Christoph

>                                         ---Tim
>
> +--------------------------------+-------------------------------------+
> | R. Timothy Edwards (Tim)       | email: tim@opencircuitdesign.com    |
> | Open Circuit Design            | web:   http://opencircuitdesign.com |
> | 19601 Jerusalem Road           | phone: (240) 489-3255               |
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