On Friday, February 1, 2019, Christoph Maier christoph.maier@ieee.org wrote:
Catching up with this thread ...
On Sun, Jan 20, 2019 at 5:45 PM Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
[...]
You may be thinking of a different couple of orders of magnitude less
than the task I have in mind, here David. I am designing a quad core 800mhz design with L1/L2 cache, multi issue out of order vector processing, virtual memory and 16, 32 and 64 bit IEEE754 FP units (we may also add FP8, have to see).
ok, so what is the transistor feature size, and the required reliability and repeatability of transistor parameters in the CMOS process that supports a design of such scale?
Don't know yet. Still a long way off. However it would not be a surprise to find that one core took up the same area as a 4 core RISC design, just because of the fact that it does 4 issue FP ops.
Monster, basically.
L.