[Libre-silicon-devel] Pad cells on test wafer

Hello Hagen Have you already an idea on how the design of our pad cells will look like? How many cascaded drivers stages will the cells contain? How many ESD rings will we provide in the padframe/cells? When I remember right we decided on an active driving capability of 10mA per cell as well as an open-collector option. At least my notes here say this :-)

Cheers David