Hi, Hagen,
please provide me with the literature for the PLL, I can try to design it, as I learned electrical engineering last century :-) Maybe, I am successful.
Cheers,
Ludwig
On Thu, Jan 3, 2019 at 9:27 AM Hagen SANKOWSKI hsank@posteo.de wrote:
Hello Christoph! Hello List.
On 1/3/19 9:04 AM, Christoph Maier wrote:
But yes, transfer gates are feasible, on the wish list and you'll get them as soon as the PMOS and NMOS are characterized with PearlRiver :-)
Isolated bulk and high voltage switches for charge pumps etc. are also insteresting ... as later step.
You can see what we already have for PearlRiver here: https://github.com/chipforge/PearlRiver/tree/master/Library/magic
In this Library Directory are
high voltage Mosfets
- L500_HVNFET_W108_L22_params.mag
- L500_HVPFET_W108_L22_params.mag
isolated Mosfets, Ferec voted for
- L500_NMOSi_W10_L10_params.mag
- L500_NMOSi_W20_L20_params.mag
- L500_NMOSi_W3_L2_params.mag
- L500_NMOSi_W3_L3_params.mag
- L500_NMOSi_W3_L8_params.mag
- L500_NMOSi_W40_L40_params.mag
- L500_NMOSi_W5_L5_params.mag
- L500_NMOSi_W8_L3_params.mag
- L500_NMOSi_W8_L8_params.mag
BJT
- L500_NPN1.mag
- L500_NPN2.mag
- L500_PNP1.mag
- L500_PNP2.mag
isolated NPN BJT
- L500_NPNi1.mag
- L500_NPNi2.mag
BTW, all sizes are in Lambda (as half the feature size Lambda is 500nm), hence the L500 in the file names.
Let's play :-) _______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel