Hi from San Diego!
I'll probably just have arrived in Oslo for a trial lecture (subject: How to deal with mismatch in IC design processes) and will be too busy travelling to make it to the Mumble ...
On Thu, Mar 7, 2019 at 4:44 AM David Lanzendörfer david.lanzendoerfer@lanceville.cn wrote:
Hi all Today we've prepared the wafer for the RTP steps we're going to perform. If successful it will reduce the resistance of the polysilicon from a few Mega-Ohm to a few 100 Ohm per square.
but a high resistive poly option sounds really useful. How good would the matching be, and what would be the dominant causes of systematic deviations from resistance as drawn?
This is a required step on our way to provide FETs with a threshold voltage of 0.8V/-0.8V
Hmmm. How so?
I'll update you tomorrow and we will discuss the results on Sunday.
Wish Victor and me luck tomorrow!
福, 禄, 壽, and all that.
tatzelbrumm
Cheers David