26 Nov
2018
26 Nov
'18
11:52 a.m.
Oh. Okey. Well. Andreas is working on something similar: https://murmur.libresilicon.com/lsc/rocket-chip-yosys
Also, yeah, making a schematics out of verilog is a bit tricky, because you've gotta place the parts from the graph in the schematics and draw the wires without it becoming a total mess. But when graphviz is satisfying anyway, I'm happy :-)
Cheers David
On Monday, 26 November 2018 7:03:00 PM HKT Luke Kenneth Casson Leighton wrote:
ah ha! i discovered yosys "show", which converts to graphviz dot-format. good enough.
yosys> read_verilog file.v yosys> show
coooool
l.