19 Nov
2018
19 Nov
'18
8:05 p.m.
Hello David, I reviewed the layout and there is an error in magic. In the cell L500_NMOSi_W3_L3_params, there is a "hole" in nwell and pbase between the FET and the edge of the source contact. I corrected it and pushed it to my repo. Please pull and re-generate the GDSII. Regards, Ferenc
On Mon, Nov 19, 2018 at 3:13 PM David Lanzendörfer < david.lanzendoerfer@o2s.ch> wrote:
Hi all After yesterdays Mumble session I've now added the missing structures Ferenc has pointed out. Please everyone look over the GDS2 file, if no more mistakes have occured I'd say we can go and order it.
https://github.com/libresilicon/PearlRiver/blob/master/Layout/gds/PearlRiver...
Cheers David