And talking about the snapback, likely the process implant steps may need to be tuned to get a proper snapback voltage. Unfortunately that is where my knowledge stops. ESD development was done in imec in a totally separate group and I was never involved with them. Test chips typically did not include ESD protection and measurements were done by properly grounded wafer probing stations.

Best to include in a next test chip an input with only the ESD clamp on it. The input should not be connected to a transistor gate as then the gate oxide may break down before you can measure the snapback voltage of the clamp.