On Wednesday, February 6, 2019, Staf Verhaegen <staf@fibraservi.eu> wrote:
Luke Kenneth Casson Leighton schreef op di 05-02-2019 om 07:34 [+0000]:
On Tuesday, February 5, 2019, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
Hi best place to ask,
Have forgotten the name of a company that has a sea of gates high end ASIC, you get to do only the one mask, the via layer. Does anyone know the company? It is apparently supported by libre design tools.
They are now Intel and not interested in low to medium volume.
Ok good to know
Second, somewhere in this talk
https://youtu.be/zXwy65d_tu8 is mentioned an open analog design project, does anyone know what that project is?
Haven't found this one yet
That's a useful one as well. However the question was more libre.
Are there any *libre* analog ASIC projects around, doing PLLs, DDR detection, differential pairs, and so on?
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