You want to diffuse! All tools to reduce the on resistance are important because
(x) better efficiency
(x) better switching (R-C lowpass formed by on-resistance and parasitic capacities)

We need to read books / documentation about cmos processes. Dont do fancy stuff
like trench FETs.
Maybe, we should also do dual gate mos-fets or tripple-gate mos-fets as this allows
us to build in AND or OR-Gates using physics:
One gate charge is not enough to open the channel, 2 charges are enough.
So you get an and gate with one transistor.

Its similar to the multi-emiter transistors in TTL which were PNP and the emiters
were at the input to be pulled to gnd (pull at least one emitter to get the transistor switched on)



On Sun, Mar 4, 2018 at 12:37 PM, David Lanzendörfer <david.lanzendoerfer@o2s.ch> wrote:
Ok!
Thanks a lot!
I will update the document accordingly!

greets
        David

On Sunday, 4 March 2018 7:22:18 PM HKT Staf Verhaegen wrote:
> David Lanzendörfer schreef op zo 04-03-2018 om 00:39 [+0800]:
> > Hi
> > Should I diffuse the p-well instead of just ion implanting it?
> > It will take another 12 hours, but the on-resistance would be much lower,
> > which will give less losses in the device.
>
> General comment is that resistance is not about power efficiency. Power
> efficiency is in CMOS related to the capacitances that are charged and
> uncharged (e.g. P = C.f.V^2/2). The resistance determines how fast you
> can go.
> Too high well resistance increases the risk for latch-up problems
> though.
>
> greets,
> Staf.


--
Best regards

CEO, David Lanzendörfer
Lanceville Technology
22A, Block2, China Phoenix Mansion,
No.2008 Shennan Boulevard,
Futian District, Shenzhen
_______________________________________________
Libre-silicon-devel mailing list
Libre-silicon-devel@list.o2s.ch
http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel