Hello List!

On 12/22/19 1:51 AM, Luke Kenneth Casson Leighton wrote:

> none aaat aaaaaalll.  analog/mixed signals were veeery specifically
> and deeeliberately left *out* of the proposal entirely.
>
> the only analog/mixed signal designing that will occur is for DDR GPIO
> pads.  even analog PLLs is highly likely to get left out, unless
> someone can demonstrate that it's absolutely essential.

It is.

All the Pads have a cut-off frequency somewhere above 100 MHz. When we
can run faster someday with smaller nodes, without a PLL, we could not
tune up the clock frequency above this cut-off frequency.