On Mon, Jun 25, 2018 at 6:21 PM, David Lanzendörfer david.lanzendoerfer@o2s.ch wrote:
Hi
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
We've discussed this project yesterday and I strongly suggested to get you on board for layouting high-frequency PCBs in case we need to do a demo FPGA board for your customers. Because you've got the experience from the EOMA board project.
yes i can handle high-speed differential-pairs, now, i know the rules about doing proper impedance matching, and how to create the clearance rules. also i can happily do power-tracks (PMICs), and general layout, no problem.
what i *can't* do is DDR3/DDR4 layouts. or, i can... but you should expect it to take several months and require several iterations. really *really* good people cost around $5k-$10k in china and they can do DDR3 layouts in about 3 weeks flat.
the absolute absolute best teams have access to ultra-expensive simulation software that's specially designed to check DDR3/DDR4 layouts. they're... hell, frankly. DDR4 has got to the point where the length of the bond-wires and the layout of the PCB *inside the fucking chip* has to be taken into account.
l.