[Libre-silicon-devel] turning verilog into graphical layout (PCB component style)

hi,

are there any tools that will take verilog and generate something akin to a PCB "component" plus show a set of "unrouted nets"?

i would like to get a visual feel for what a design looks like, and a conversion of verilog to "blocks" is the easiest way i can think of.

l.