Re: [Libre-silicon-devel] NLNet grant approved

Hello Luke.

On 12/22/19 7:04 AM, Luke Kenneth Casson Leighton wrote:

On Sunday, December 22, 2019, Hagen SANKOWSKI <hsank@posteo.de mailto:hsank@posteo.de> wrote:

Hello List!

On 12/22/19 1:51 AM, Luke Kenneth Casson Leighton wrote:

> none aaat aaaaaalll.  analog/mixed signals were veeery specifically
> and deeeliberately left *out* of the proposal entirely.
>
> the only analog/mixed signal designing that will occur is for DDR GPIO
> pads.  even analog PLLs is highly likely to get left out, unless
> someone can demonstrate that it's absolutely essential.

It is.

All the Pads have a cut-off frequency somewhere above 100 MHz. When we
can run faster someday with smaller nodes, without a PLL, we could not
tune up the clock frequency above this cut-off frequency.

ok.   so, from somewhere, we need a libre licensed PLL. is one in development somewhere?

is it worth putting in an extra (small) NLNet grant application for?

The Issue I see - we have to bring back David into the Clean Room first. 'Cause PLLs are quite heavy analog Voodoo stuff and strongly depending on the technology they are using. IMHO we can not re-use a PLL developed for one technology on another technology.

So our goal has to have first the LibreSilicon PDK. Than, with this PDK we can design a PLL which could work for other LibreSilicon PDK users also.

Regards, Hagen.