No, bit banging with ram, no way! I had enough problems with a company whiche used gpio bit banging with a dsp )to read a fast ADC (What you dont fetch gets overwrittwn.)
I
On July 18, 2021 9:39:53 PM GMT+02:00, "David Lanzendörfer" leviathan@libresilicon.com wrote:
Hi So today we've been talking about ways around having to use DDR3/DDR4 interfaces for external memory of a potential SoC but as it turns outs, all our candidates like HyperRAM or MRAM are out of the window because of the prices. As usual I came back to the question "is it possible to do this with an AVR?" which usually helps me at fixing such problems and I came across those projects here: https://www.circuitlake.com/interfacing-dram-memory-with-avr.html https://github.com/jnk0le/AVR-DRAM Turns out that it's possible to speak to DRAM over a DDR3 without a special controller, just over GPIO. They got an Atmega to access a Hitatchi M5M44800. The RAM access will be slow, but we don't need to know about the analog properties of the process in order to achieve this. I will probably implement this for my test SoC on a CPLD. Hagen will explain more in the follow up/minutes.
Cheers -lev
On Saturday, July 17, 2021 11:49:14 AM WEST Hagen SANKOWSKI wrote:
Hello List!
This is our weekly announcement for the next Mumble Sessions on
Sunday
2021-07-18 @ 18:00 UTC.
Please join us as usual at our Mumble Server murmur.libresilicon.com
at
Port 64738, the Channel is IC.
We like to follow-up our topics from mumble sessions before.
Regards, Hagen. _______________________________________________ Libresilicon-developers mailing list Libresilicon-developers@list.libresilicon.com
https://list.libresilicon.com/mailman/listinfo/libresilicon-developers
-- (__/) (='.'=) This is Ninja Bunny. (")_(") Copy and paste Bunny into your signature to help him gain world domination
Libresilicon-developers mailing list Libresilicon-developers@list.libresilicon.com https://list.libresilicon.com/mailman/listinfo/libresilicon-developers