On Wed, Jan 2, 2019, 15:40 ludwig jaffe <ludwig.jaffe@gmail.com wrote:
Hi all,
we should prototype all kinds of components, capacitors, resistors, bipolar transistors and mos transistors, in order to get a protfolio of parts, there parts need to be identified, so we get a spice model for them. Remember, all parts are analog, even nand gates. You can use 4000 cmos logic to build bad amplifiers, just by having feedback resistors likewise with op amps.
So the process guys should try to make as many as possible parts on a wafer to get a parts lib.
Then we can build circuits like SAR or Delta Sigma ADC. A flash ADC with 8 bit would be funny but not that fast, but why not.
And always remember, our chips are not the fastest but the biggest :-)
Unless one or two of us here have a neuromorphic / translinear circuit bucket list and access to bespoke process parameters, right, Mr. Potbox?
Tatzelbrumm
Cheers,
Ludwig
On Wed, Jan 2, 2019 at 2:57 PM Tim Edwards tim@opencircuitdesign.com wrote:
Hello Christoph,
First things first: What are appropriate test structures (like, transistor, resistor, and capacitor arrays) that allow us to characterize devices AND device matching in a way to allow meaningful analog/mixed signal design? I would assume that you already have put quite a bit of thought into this, if and when a really open silicon process ever became available (like, now, with these crazy guys here). I'm not sure yet (and open to whatever suggestions I could get from People Skilled In The Art) what ADC topologies would be suitable to try out.
I have thought about this much less than you seem to think. I have never built up a fabrication process from scratch like the Libre Silicon guys. So test structures that go in the margins of wafers are things that I have a basic understanding of, but I am more familiar with analyzing the measurement results than with thinking about how the structures should be designed and how to make the measurements in the first place.
Best capacitor matching for ADCs generally comes from MiM capacitors, 2nd best from poly-poly capacitors, and for smaller feature sizes where the layer thickness is on par with the metal width and spacing rules, fingered MoM caps are probably 3rd best. Common centroid geometry with dummy devices on the periphery is a must. Beyond that, it really depends on what's being offered in the process.
ADC topology depends more on the application than anything else. My preference is Sigma-delta with digital filtering, but sometimes an SAR is called for. I've never seen anyone do flash ADCs in practice.
IIRC, efabless has venture capital, so what are the strings (i.e., exclusive representation rights or some such) attached to importing designs and PDKs into your infrastructure?
Actually, no, efabless is not funded by venture capital. We are currently funded by a group of three people, one of whom is the CEO (Mike Wishart) and the other two long-time Silicon Valley startup founder types (Lucio Lanza and Jack Hughes). We are looking for additional investment from companies who can benefit from having IP in our catalog listings, or benefit from the web-based collaboration tools.
For now, I just established mumble communication with Hagen and Leviathan, and next I'm planning to dig into the gds, and how to use the magic et al. tool suite. I'll pester you with questions about your tools to the extent you'll let me.
I am always happy to answer questions. Users are the lifeblood of open source tools, and must be kept happy. . .
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