Hi,

I just found something in Sam Zeloof's latest design (08/2021) that I overlooked first and I'm not sure if it has been discussed here yet... He uses wafers which are pre-doped for p-wells, and gate oxide and polysilicon pre-applied without any mask. He then patterns, etches and n-dopes source/drain regions, using the poly as a mask and then adds "hard-baked photoresist as a dielectric" to separate the poly gate from the above metal layer. This requires some changes in the process and will only allow n-type transistors, but he completely avoids the problems with poly deposition AND doesn't have to grow field oxide -- so I'm actually not sure if he needs a high-temp furnace at all.

Link: top article on http://sam.zeloof.xyz/category/semiconductor/

Opinions?

Greetings,

Martin