Hi
I'll do my very best :-)
Great! Thanks!
Additional results from the meeting today: Also these folks have an issue with us publishing their recipes for depositing Polysilicon and so on. So we will have to develop our own recipes if we wanna publish recipes.
Also HKUST raised the rent price per year a bit... I've checked with eFabless whether they wanna contribute to the R&D cost but haven't gotten feedback yet.
Also Shuyun (Dr. Zhao) repeatedly raised concerns about the reproducibility because of contaminations within the clean room. She doubts that we can build a whole CPU core in their lab...
But honestly I think the point she brought up only make sense to consider when making mass manufacturing of MCUs/CPUs/SoCs, and for that we have anyway other partners, so I don't worry too much about this point.
The CMP maximum deviation is around 5 micro meters... this might pose a problem with the depth control of the box isolation.
Also, we have to reduce the depth of the box isolation.
How deep do we wanna make the nwell and pwell? 4 micro meter? And the STI? 2 micro meter?
That should be enough to get working ESD lateral diodes.
Cheers David
On 03/22/2018 01:10 PM, David Lanzendörfer wrote:
Hi The probe is placed manually. The diameter of the pin is 20 micro meters.
@Hagen: That means our pads should be at least 40x40 micrometer I guess. And don't forget that our minmum line spacing is 500nm! Better make 1um spacing!
Cheers
David
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