Hello,

I had a quick look at the current PearlRiver design(s). I also see layout not schematics or netlists. Do you plan to simulatie your measurement procedures before actually manufacturing the wafer ?

Normal design procedure for analog (test) circuits is first do schematic capture, simulate the test procedure and then make layout according to schema and make it LVS (layout-versus-schematic) clean.

Specifically for the L500_MOSFET_aligning structure which is indicated to also be used for measuring resistance and capacitance.

To save pins I see a lot of pins are shared. For example I see that the middle pin is both connected to NWELL as to PSUB/PWELL which seems dangerous to me.

In general I see that almost all of the pins are in one way connected to NWELL or PSUB/PWELL and basically shorted with other pins through these wells and also metal1. So I am wondering which resistances you actually try to measure here.

greets,

Staf.