All,
I do think the device list seems to get good and I don't have time to do detailed view.
One thing I wonder is if you guys have thought about which in-line measurements during the processing you want to do and with which tools you will do them ?
For example on the test design I did at imec there were always overlay measurement structures for each litho step so you could measure the overlay. For all steps where resist was used to etch there were cross section structures
I have also seen the silk layer that contains some artwork and labels. When looking at the magic tech file it only seems to be put on the metal3 layer. I would put it on all the metal layers and on sti and gate layer. When you want to look for example at transistor on an electron microscope, you will need to do after gate etch and then you will be happy to have the labels. otherwise it will very difficult to know at which transistor you are looking.
Also for the via layer you may want to put some unique labels somewhere.
greets,
Staf.
Hagen SANKOWSKI schreef op ma 05-11-2018 om 10:01 [+0100]:
Hello Everybody!
According our mumble session yesterday I now rectified the
'PearlRiver_die'. [0]
Changes are:
- size is now 4.3 x 4.3 mm^2
- long 2000 R-Square lines for NWELL, PWELL, NBASE and PBASE are added
around the edges
- all tables inside pearlriver_quarter are cramed
Yesterday we also talked about the mosfet-alignement structure, which is
still in the repository, but was recently gone off die. With changes
today we have sufficient space for adding again.
Still missing from my point of view are the diodes
- substrate -> nwell,
- pbase -> nwell,
- pdiff -> nwell.
This is work-in-progress.
Please look at the structures and find the issues and send your comments
and changes regarding the PearlRiver Testwafer ASAP at least to the list
or via pull-requests on github.
We are close before review - we like to order the masks a week later!
Best Regards,
Hagen
[0] https://github.com/chipforge/PearlRiver
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