Hi all scale it up.
I would make it bigger, lets say 4 micron as the circuit is more reliable with bigger transistors, so it survives misuse to a higher degree and as the 555 is not so complicated one could use more chip area.
It would be good to be at least compatible with 4000 cmos logic which works upto 20v. If the 555 survives 30v it wkuld be an interesting feature.
Also have big output transistors so one can directly drive a big mosfet with a big gate capacity.
So one can do pwm with a mosfet and our 555 to control dc motors or to build simple switchmode power supplies.
Cheers Ludwig
On Thursday, May 2, 2019, Hagen SANKOWSKI <hsank@posteo.de> wrote:
> Hello List!
>
> I just add two more versions of the 555 schematic to the
> github.com/libresilicon/CMOS-555 repository.
>
> One is based on reversed-engineers work, published on righto.com; I took
> the same number scheme for the circuits.
>
> Another is from the already mentioned Book "Designing Analog Chips" from
> Hans Camenzind, the original author of the 555. On page 148 he shows a
> schematic for a 5V CMOS version. Well, this schematic is literally
> similar to the Wikimedia Version. I called this the "Book Version" and
> took also Hans number scheme (and dimensions!).
>
> So, here we got an issue. The Version showed by Hans is for 5 Volt he
> wrote. And, this version uses a feature size of 0.5 Microns on some
> MOSFETs which is smaller than our 1 micron technology.
> I think, we have to scale-up the dimensions for two reasons.
>
> 1. We do not get the right values from PearlRiver to calculate beta
> right; 1 micron for L and 1.5 for W is the minimum we can measure on
> PearlRiver.
>
> 2. The version is aimed for 5 Volt. If we like to run with higher supply
> voltage for reasons, we have to enforce the gate length.
>
> @Tatzelbrumm, @Ference, what do you think about that??
>
> Regards,
> Hagen Sankowski
>
> P.S.: The
>
--
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