Hello Everyone,
As per the last mumble session, my recommendations for debugging are the following:
Test subject: a native NMOS from the nmos table (no isolation/HV/etc., as only the basic layers were done).
Specific measurements:
- Diode characteristization (V-I curve) between source-bulk, while all other terminals left floating. Aim: check metal1 and contact continuity, check doping. Expected result: diode-like behavior. Possible failures: linear I-V curve (faulty doping), no current flows at all even when source is more negative than bulk (broken metal1, broken contact)
- Diode characteristization (V-I curve) between drain-bulk, while all
other terminals left floating. same as above.
- V-I curve between source-drain, while gate and bulk tied to source (not to be performed if poly proves to be broken). Aim: check if end of the poly gate is indeed extending over fox edge (concern due to unexpected fox over-etch). Expected result: no current flows while drain is more positive than source. Possible failures:
linear I-V curve (not enough overlap causes "bridging" between S-D).
The same may be done on a PMOS as well (just with opposite polarities).
Regards,
Ferenc