Hello Hagen Have you already an idea on how the design of our pad cells will look like? How many cascaded drivers stages will the cells contain? How many ESD rings will we provide in the padframe/cells? When I remember right we decided on an active driving capability of 10mA per cell as well as an open-collector option. At least my notes here say this :-)
Cheers David
Hello David!
On 07/21/2018 04:05 PM, David Lanzendörfer wrote:
Have you already an idea on how the design of our pad cells will look like?
Yes, I do have a glue..
How many cascaded drivers stages will the cells contain?
This I like to calculate later, when we know more about our transistor capabilities - and can estimate W / l for dedicated precise amplification factor. That's why different transistor structures on our test wafer are in urgent need.
How many ESD rings will we provide in the padframe/cells?
At least two, one with GND (connected to p-Substrate) and one with VDD IO Supply (connected to n-well).
When I remember right we decided on an active driving capability of 10mA per cell as well as an open-collector option. At least my notes here say this :-)
Yes, this is the target I am working on. I like to check in more stuff soon :-)
Regards, Hagen.
On Saturday, July 21, 2018, Hagen SANKOWSKI hsank@posteo.de wrote:
Hello David! ).
When I remember right we decided on an active driving capability of 10mA
per
cell as well as an open-collector option. At least my notes here say
this :-)
Yes, this is the target I am working on. I like to check in more stuff soon :-)
10mA wont drive sdmmc full speed, or other hi speed 125mhz interfaces
Regards, Hagen.
Hello Luke.
On 07/21/2018 05:47 PM, Luke Kenneth Casson Leighton wrote:
Yes, this is the target I am working on. I like to check in more stuff soon :-)10mA wont drive sdmmc full speed, or other hi speed 125mhz interfaces
You are right. We currently working on our Test Wafer - this becomes our first free silicon at all. If you like to play with the Magic Tool, you can already check some test structures here: https://github.com/chipforge/PearlRiver inside the directories of Library/magic and Layout/magic.
Feedback welcome!
We have to characterize all stuff on silicon like resistance / capacitance on different layers first, than put the values back to the Spice model before we can calculate accurate transistor parameters for cells and pads.
Your wish with multiplexed IO cells is still on the to-do-list. And the roughly calculated 10mA driving output cell is for impressing / attracting more people. They like blinking LEDs ;-) - et voilà we do so with on output on the test chip.
Regards, Hagen.
On Saturday, July 21, 2018, Hagen SANKOWSKI hsank@posteo.de wrote:
.
Your wish with multiplexed IO cells is still on the to-do-list.
I can take care of the mux side, the io cells noot so much.
And the roughly calculated 10mA driving output cell is for impressing /
attracting more people. They like blinking LEDs ;-) - et voilà we do so with on output on the test chip.
Ta-daaaa :)
Oh look up online conference. Vsdopen conference.
Hi
Your wish with multiplexed IO cells is still on the to-do-list.
I can take care of the mux side, the io cells noot so much.
We will develop pad cells and drivers able to wire the periphery we have in the core actually out into the real world. That's our job. Then we ship a box or as many the customer orders to the location of the customer where the customer can solder the chips onto a PCB, or put it into a bowl with milk and eat it for breakfast or whatever they like to do with it. As soon as we've shipped the product and provided the data sheet it's not our business anymore what the customer will do with the product. We will however offer assistance in developing end-user products with the products we provide for a decent fee per hour :-)
And the roughly calculated 10mA driving output cell is for impressing / attracting more people. They like blinking LEDs ;-) - et voilà we do so with on output on the test chip.
Exactly. Customers and investors like blinky blinky tactile demos. It's easier to attract the attention of average people this way :-)
Ta-daaaa :) Oh look up online conference. Vsdopen conference.
Well... They're not developing a Libre process... I hope I can make a pretty real life conference appearance showcasing the Pearl Rive end of this year at the Chaos Communication Congress :-)
Cheers -lev
On Saturday, July 21, 2018, David Lanzendörfer david.lanzendoerfer@o2s.ch wrote:
Ta-daaaa :) Oh look up online conference. Vsdopen conference.
Well... They're not developing a Libre process...
They wre in chenai saw talk invited oeopke using and develioung libte silicon tools and priduxcts to showcase.
Hi Hagen How many metal layers should I plan for the process I'm going to submit soon? BTW: Yesterday I've written the last exam for the chemical safety certificate. I also submitted my passport photo, so I should get my access card to the lab within the next few days.
Cheers David
On Sunday, 22 July 2018 12:02:58 AM HKT Hagen SANKOWSKI wrote:
Hello Luke.
On 07/21/2018 05:47 PM, Luke Kenneth Casson Leighton wrote:
Yes, this is the target I am working on. I like to check in more stuff soon
10mA wont drive sdmmc full speed, or other hi speed 125mhz interfaces
You are right. We currently working on our Test Wafer - this becomes our first free silicon at all. If you like to play with the Magic Tool, you can already check some test structures here: https://github.com/chipforge/PearlRiver inside the directories of Library/magic and Layout/magic.
Feedback welcome!
We have to characterize all stuff on silicon like resistance / capacitance on different layers first, than put the values back to the Spice model before we can calculate accurate transistor parameters for cells and pads.
Your wish with multiplexed IO cells is still on the to-do-list. And the roughly calculated 10mA driving output cell is for impressing / attracting more people. They like blinking LEDs - et voilà we do so with on output on the test chip.
Regards, Hagen.
Hello.
On 07/21/2018 07:38 PM, David Lanzendörfer wrote:
Hi Hagen How many metal layers should I plan for the process I'm going to submit soon?
Well, I like to deal with up to three metal layers, not more.
I would guess, that two metal layers are comfortable and reasonable. Regarding the metal processing I would give metal3 also a chance on Pearl River.
My assumption is, that the 5um CMP accuracy will bite us in the ass with metal3 already.
So let's try with 3 metal layers for PearlRiver. If we only get 2 layers functional, we are still fine - standard cell design mostly still route-able.
Regards, Hagen.
Hi
Well, I like to deal with up to three metal layers, not more.
Okey!
I would guess, that two metal layers are comfortable and reasonable. Regarding the metal processing I would give metal3 also a chance on Pearl River.
Okey!
My assumption is, that the 5um CMP accuracy will bite us in the ass with metal3 already.
For now, because we use Aluminum interconnect, we don't have to use CMP. And the CMP at RCL Semi in Tai Po will have not only copper interconnect capabilities but a CMP machine better equipped to adequately planarize the oxide.
So let's try with 3 metal layers for PearlRiver. If we only get 2 layers functional, we are still fine - standard cell design mostly still route-able.
I expect no problems with the 3 metal layers, because the Aluminum can easily be etched with the Aluminum etcher.
Cheers David
On 07/21/2018 08:54 PM, David Lanzendörfer wrote:
So let's try with 3 metal layers for PearlRiver. If we only get 2 layers functional, we are still fine - standard cell design mostly still route-able.
I expect no problems with the 3 metal layers, because the Aluminum can easily be etched with the Aluminum etcher.
Okay, the PearlRiver Test Structures are using up to three metals. Let's have a look at the results.
Regards, Hagen.
For anything to do with muxing ie general purpose pu/ pd plus pp/od plus 10/20/30/40mA all as options all needed along with speed filters. Level shifting builtin also really needed. Same pins get used for i2c spi sdmmc rgb/ttl some of those are 9600 baud some as high as 125mhz esp RGMII.
Level shifting needed because core IO voltage may be 0.7 on 22nm or 1.1 1.2 on 45nm or 1.8v on 180nm and IOpad anywhere from 1.2-1.8v on mobile systems right the way to 1.8-3.3v for 180nm. Typically level shifting is in those 2 ranges, v rare to see 1.2v all way to 3.3v
On Saturday, July 21, 2018, David Lanzendörfer david.lanzendoerfer@o2s.ch wrote:
Hello Hagen Have you already an idea on how the design of our pad cells will look like? How many cascaded drivers stages will the cells contain? How many ESD rings will we provide in the padframe/cells? When I remember right we decided on an active driving capability of 10mA per cell as well as an open-collector option. At least my notes here say this :-)
Cheers David
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David Lanzendörfer -
Hagen SANKOWSKI -
Luke Kenneth Casson Leighton