Hello Everyone,

Meeting minutes of the Mumble session:

- Setting up a mediawiki instance to store process flows and semiconductor manufacturing-related know-how. Also functions as a knowledge base for the users of LS50U

- Chemical safety precautions shall be written for LS50U (product liability...).

- Use polysilicon gate for LS50U. Solution to exclude ionic contamination during gate oxide growth and deposit poly without silane gas: purchase wafers with gate-oxide and poly predeposited and pattern that. Possibly order and stock them. Ref: Sam Zeloof's second IC

- Use the first process layer (diffusion) patterning to create alignment marks for subsequent exposures (first layer needs not to be aligned to anything)

- Solution for CVD deposition of field oxide: use a resident layer of patterned and hardbaked photoresist as the dielectric layer. Ref: Sam Zeloof's second IC

- Structured milestone plan has to be established. First priority: get the patterning work, test it with resist and developer. Actual process steps (diffusion, etching, etc...) come after that.

Regards,

Ferenc

On 15/08/2021 18:02, David Lanzendörfer wrote:

Howdy So I suggest, now that we came to the conclusion that I should really follow the law in a broader sense when it comes to developers and resists, and etching, I decided to go Sam's route and use AZ 4210 with KOH as developer and run a magnetron design from Hack A Day in reverse for the etching process.

Lets discuss that :-)