Hi all Today we've prepared the wafer for the RTP steps we're going to perform. If successful it will reduce the resistance of the polysilicon from a few Mega-Ohm to a few 100 Ohm per square. This is a required step on our way to provide FETs with a threshold voltage of 0.8V/-0.8V I'll update you tomorrow and we will discuss the results on Sunday.
Wish Victor and me luck tomorrow!
Cheers David
Hi from San Diego!
I'll probably just have arrived in Oslo for a trial lecture (subject: How to deal with mismatch in IC design processes) and will be too busy travelling to make it to the Mumble ...
On Thu, Mar 7, 2019 at 4:44 AM David Lanzendörfer david.lanzendoerfer@lanceville.cn wrote:
Hi all Today we've prepared the wafer for the RTP steps we're going to perform. If successful it will reduce the resistance of the polysilicon from a few Mega-Ohm to a few 100 Ohm per square.
but a high resistive poly option sounds really useful. How good would the matching be, and what would be the dominant causes of systematic deviations from resistance as drawn?
This is a required step on our way to provide FETs with a threshold voltage of 0.8V/-0.8V
Hmmm. How so?
I'll update you tomorrow and we will discuss the results on Sunday.
Wish Victor and me luck tomorrow!
福, 禄, 壽, and all that.
tatzelbrumm
Cheers David
Hi from Hong Kong ;-)
Today I found the solution for our problem (on page 443): https://www.researchgate.net/publication/235643063_Reduction_of_the_C49-C54_...
We've got to anneal our wafer after the C49 formation for at least 42 minutes at at least 725 degree Celsius.
So tomorrow, we prepare a sample and process it this way.
I guess the Mumble session tonight will be pretty short anyway ;-)
Cheers David
Hi from San Diego!
I'll probably just have arrived in Oslo for a trial lecture (subject: How to deal with mismatch in IC design processes) and will be too busy travelling to make it to the Mumble ...
Hi from Oslo!
So, it turned out that ...
On Thu, Mar 7, 2019 at 3:48 PM Christoph Maier christoph.maier@ieee.org wrote:
Hi from San Diego!
I'll probably just have arrived in Oslo for a trial lecture (subject: How to deal with mismatch in IC design processes) and will be too busy travelling to make it to the Mumble ...
I arrived in Oslo just in time to join the Mumble (and distract my hostess with the Mumble talk, and then, by accident, y'all with my chat with the hostess)
Now that the trial lecture is done, I changed its repository status to "public": https://bitbucket.org/cmucsd/analogdesignlecture/
Next question: Y'all, i.e., the people on this list interesed in a freely accessible silicon IC process, are also part of the target audience of this lecture, in the sense that it should set a few things straight what is feasible in analog IC design and what isn't.
What added information would help clarify for you that analog IC design comes with specific problems, that require specific design patterns to overcome them.
Also, David, what would be a good URL to put yet another clickable hyperlink easter egg to your process description into the PDF, where I pasted in your process cross-section?
Catching up with a week of sleep deficit, Christoph
libresilicon-developers@list.libresilicon.com
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Christoph Maier -
David Lanzendörfer