There are a couple of MOSFET Models available, the last one I came across was BSIM4 (for deep-sub-Mircon <100 nm) and BSIM3 which ought to be good enough down to 180 nm.
@David, your Simulator uses the most simplest (and fastest) Model which is know as a first generation model for default.
So, the 3rd generation model, quite more complicated has a couple of more parameters to tune. Here is the documentation from ngspice, btw. the best FOSS spice simulator we can use.
http://ngspice.sourceforge.net/external-documents/models/bsim330_manual.pdf
We need reasonable values for *all* parameters!
BTW: I just had the enlightenment about thresholds vs. internal vs. external power supply! Of course we can just set the internal voltage to 2.8V, then we're totally fine with V_Tn=0.8V and V_Tp=-0.8V And we of course also put that rail at the Input-Pad. The only trouble will be to convert the 2.8V logic levels to the TTL 5V when emitting it at the output-pad-cell. But that's the reason why they are so fucking big and complicated usually.
Yey! I got it, just while walking to the Mexian restaurant to get me some dinner. ^_^
I will put some explenations into the document.
And now I will tackle SPICE! Thanks for the link!
Cheers David
On Monday, 5 March 2018 5:22:42 AM HKT Hagen SANKOWSKI wrote:
There are a couple of MOSFET Models available, the last one I came across was BSIM4 (for deep-sub-Mircon <100 nm) and BSIM3 which ought to be good enough down to 180 nm.
@David, your Simulator uses the most simplest (and fastest) Model which is know as a first generation model for default.
So, the 3rd generation model, quite more complicated has a couple of more parameters to tune. Here is the documentation from ngspice, btw. the best FOSS spice simulator we can use.
http://ngspice.sourceforge.net/external-documents/models/bsim330_manual.pdf
We need reasonable values for *all* parameters! _______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
Well,
On 03/05/2018 01:21 PM, David Lanzendörfer wrote:
BTW: I just had the enlightenment about thresholds vs. internal vs. external power supply! Of course we can just set the internal voltage to 2.8V, then we're totally fine with V_Tn=0.8V and V_Tp=-0.8V And we of course also put that rail at the Input-Pad. The only trouble will be to convert the 2.8V logic levels to the TTL 5V when emitting it at the output-pad-cell. But that's the reason why they are so fucking big and complicated usually.
Well, they get "so fucking big" while they have to drive current.. sorry for disturbing your moment of Enlightenment a little bit. Internally, we can let drive our Standard Cells by u-Amperes (and saving power of course, every switching activity means charge or discharge the capacitance behind cells). But to drive outside something like a fancy LED we need current in m-Amperes, which is at least two or three dimensions bigger. How to drive big current? By making W and L of transistors much, much bigger and really huge.
And, for changing switching levels (low Vdd < > high Vdd) there are so called level-shifter. You might been came across while have signals on PCBs which has to cross different power levels. Mainly, level shifter are just low-Drain-Source-R Transistors between both domains and are working in both directions.
So we are internally absolute free, just placing our level shifter between the core-logic and the Io-logic; there's no problem.
Yey! I got it, just while walking to the Mexian restaurant to get me some dinner. ^_^
I will put some explenations into the document.
Well, I think, this kind of essentials needs something like a side-channel. It is definitively not the stuff I would expect in the *Process*-Document. Also mentioned the IO-Level figures and explanation do you already have there. This is something I would place in a (Standard Cell and CMOS) wiki where every rookie can get the background he/she is still missing. But it does not belong to the process.
And now I will tackle SPICE! Thanks for the link!
Your are welcome
Ok! So we can do the following for Input and Output buffers: We can use multiple stages for the input and for the output and can then make sure, that at the input 0.8 V V_off and 2V V_on are met, by having a cascade of these TTL interface inverters. I think that's the reason why there is "so much stuff" inside the input cell.
We can use the p-load to make the VDD drop to a level where 2V is being detected as high. (VDD=2.8V) Then we make multiple stages until we're at the level of the actual VDD rail (5V)
Well, I think, this kind of essentials needs something like a side-channel. It is definitively not the stuff I would expect in the *Process*-Document. Also mentioned the IO-Level figures and explanation do you already have there. This is something I would place in a (Standard Cell and CMOS) wiki where every rookie can get the background he/she is still missing. But it does not belong to the process.
Ok! I will then just add target parameters for the V_Tp and V_Tn and will just reference to the implementation of the standar cells in you repo.
Cheers! David
On Monday, 5 March 2018 8:53:53 PM HKT Hagen SANKOWSKI wrote:
Well,
On 03/05/2018 01:21 PM, David Lanzendörfer wrote:
BTW: I just had the enlightenment about thresholds vs. internal vs. external power supply! Of course we can just set the internal voltage to 2.8V, then we're totally fine with V_Tn=0.8V and V_Tp=-0.8V And we of course also put that rail at the Input-Pad. The only trouble will be to convert the 2.8V logic levels to the TTL 5V when emitting it at the output-pad-cell. But that's the reason why they are so fucking big and complicated usually.
Well, they get "so fucking big" while they have to drive current.. sorry for disturbing your moment of Enlightenment a little bit. Internally, we can let drive our Standard Cells by u-Amperes (and saving power of course, every switching activity means charge or discharge the capacitance behind cells). But to drive outside something like a fancy LED we need current in m-Amperes, which is at least two or three dimensions bigger. How to drive big current? By making W and L of transistors much, much bigger and really huge.
And, for changing switching levels (low Vdd < > high Vdd) there are so called level-shifter. You might been came across while have signals on PCBs which has to cross different power levels. Mainly, level shifter are just low-Drain-Source-R Transistors between both domains and are working in both directions.
So we are internally absolute free, just placing our level shifter between the core-logic and the Io-logic; there's no problem.
Yey! I got it, just while walking to the Mexian restaurant to get me some dinner. ^_^
I will put some explenations into the document.
Well, I think, this kind of essentials needs something like a side-channel. It is definitively not the stuff I would expect in the *Process*-Document. Also mentioned the IO-Level figures and explanation do you already have there. This is something I would place in a (Standard Cell and CMOS) wiki where every rookie can get the background he/she is still missing. But it does not belong to the process.
And now I will tackle SPICE! Thanks for the link!
Your are welcome
libresilicon-developers@list.libresilicon.com
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Hagen SANKOWSKI