Hello Everyone,

We agreed on today's mumble session that we will follow a "modular" approach on PRNG: instead of layouting and distributing a complete chip in GDS2, there shall be certain modules from which the implementer can assemble their own test chip, customized to the technology capabilities of the fab. For example, you need Rsq for base wells and collector wells if you actually implant them, and this is also valid for HVMOS, ISOMOS and BJT devices. Similarly, You don't need to waste space for Z-diodes if you have no RTP or poly altogether.

Rationale: - PR1 is already 4x4mm2, which may not fit on all steppers of the world. With the modular approach, the implementer can take the aspect ratio and size limitations of its stepper into account. - By eliminating modules that are not needed, space can be freed up to insert new or custom test structures. - It is also possible and desirable to make the chip smaller, so edge effects on the wafer can be estimated more accurately (and more chips to measure also reduces uncertainity in statistical process control). - The modules can also be re-used to design PCM stripes or dies for live manufacturing as well...

One important thing is that the modules must have an outer dummy ring on the relevant layers, as we will no longer have control on what is placed near what. The dummy rings are aimed to ensure consistent microenvironment during processing, so layout-dependent effects will not influence the performance of individual modules, keeping results from different implementations comparable.

Regards, Ferenc

On Sat, May 9, 2020 at 9:27 PM Philipp Gühring pg@futureware.at wrote:

Hi,

Could we create larger PearlRiver like Testwafers, or is it already the largest size possible on our wafers?

I would like to add some more structures on PearlRiver. Can I just enlarge it, or do I have to replace things? What would be the maximum size?

According to David: "ideally we wanna make the next PearlRiver even smaller, rather than bigger, because the more dies you can fit on one wafer the better you can characterize issues with edge effects" What we could do is splitting the test structures across multiple test wafers based on the complexity level a lab can do. If a lab can't build polysilicon for instance, it's pointless for them to test polysilicon zener diodes."

My idea at the moment is to build a Test Wafer generator which would help us there.

Lets try to discuss this tomorrow in the Mumble call.

Best regards, Philipp _______________________________________________ Libresilicon-developers mailing list Libresilicon-developers@list.libresilicon.com https://list.libresilicon.com/mailman/listinfo/libresilicon-developers