Hi The following points resulted from yesterdays Mumble Session on May 27, 2018: We've discussed the need for a finalization of the test structure documentation in order to start drawing the test wafer layout. This task has been taken over by Hagen, please contact him if you wanna add more test structures or take over the task (would be very appreciated!) Hagen is also working on the first revision of the design rules document. My task is to finish the first process flow to test with the machines at HKUST. Also we've discussed attack vectors through JTAG in view of future highly secure SoCs with encrypted DRAM (crypto unit withint he DRAM controller) and I'm working out a paper on the side on that topic. All together I've got a pretty good solution to prevent attacks at running systems, which is to provide a reset pin which has to be toggled at least at the begging of the communication in order to set the device into "JTAG mode" which will reset the DRAM crypto key and make it impossible to extract data stored before switching into JTAG mode. (The DI, DO flipflop only is being clocked when the "JTAG mode" bit is true) Cheers David