Hi What do you think about building the box isolation after constructing the wells? Any apparent downside on this I'm overlooking?
Cheers David
In case the CMP actually has such a shitty depth control as the folks at HKUST claimed on Thursday we might have to resort to another strategy because a variation of 5 microns makes their CMP machine unusable for the STI.
Maybe etching the STI trenches after building the n-well/p-well and before the gate, and then using another expsosure step in order to open windows in the oxide for the thin-oxide+polysilicon to touch down to the wells?
Danny? Anyone? Thoughts?
Cheers David
On Saturday, 24 March 2018 4:58:37 PM HKT David Lanzendörfer wrote:
Hi What do you think about building the box isolation after constructing the wells? Any apparent downside on this I'm overlooking?
Cheers David
Dear Danny Cedric had a phone call with HKUST today and apparently they don't know exactly what the depth precision is because apparently no one has been using their CMP machines for around 3 years or so... So my questions: a) How are the chances the machine is still working at all? b) What corrosive chemicals would you suggest in order to planarize silicon +silicon-dioxide?
But that tells us that these folks haven't done box isolation or CMOS circuitry in general in a while with these machines.
If we provide them with a working CMOS process for their machines that might actually cause a run from students trying their architecture out with the equipment, which in turn means a lot of potential new FOS IP cores being developed for the node, which we then can help with marketing and mass manufacturing along side our own products!
I smell opportunity here.
Cheers David
On Wednesday, 28 March 2018 8:32:33 AM HKT DAnny Cheung wrote:
Dear David,
I am not quite sure what the HKUST said abvout the depth control. Typically, the correct CMP system can control depth to the depth of field of lithography. within angstron level. Actually, CMP is consist of chemical and mechanical. And I am thinking they may got a wrong and corrosive chemicals. Best regards,
Danny
Sent: Saturday, March 24, 2018 at 5:29 PM From: "David Lanzendörfer" david.lanzendoerfer@o2s.ch To: libre-silicon-devel@list.libresilicon.com Cc: "DAnny Cheung" klcheung@chemist.com Subject: Re: [Libre-silicon-devel] Question: STI *after* wells? Alignment. In case the CMP actually has such a shitty depth control as the folks at HKUST claimed on Thursday we might have to resort to another strategy because a variation of 5 microns makes their CMP machine unusable for the STI.
Maybe etching the STI trenches after building the n-well/p-well and before the gate, and then using another expsosure step in order to open windows in the oxide for the thin-oxide+polysilicon to touch down to the wells?
Danny? Anyone? Thoughts?
Cheers David
On Saturday, 24 March 2018 4:58:37 PM HKT David Lanzendörfer wrote:
Hi What do you think about building the box isolation after constructing the wells? Any apparent downside on this I'm overlooking?
Cheers David
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