[Libre-silicon-devel] Netlist and LVS for PearlRiver

[Hagen SANKOWSKI]

Hello Staf.

First, I like to thank that you looked at the layout.
Second, you are right in your observations.

Yes, the L500_MOSFET_aligning MOSFET-like structure shares the same 
Ground-Pad in the middle.
And, the PAD which drives the Poly-Gate on the MOSFET-like structure is 
also shared with a DRAIN-/SOURCE-stripe.

If you look deeper into the structure (which I adapt from a german 
textbook [0]), you see that the DRAIN- and SOURCE stripe is shorted to 
one contact. So, the structure looks similar to a MOSFET transistor, but 
it isn't, and can not work as a transistor.
We like to
- see how good align we can different mask (esp. needed for MOSFETS), 
therefor they are rotated by 90 degree.
- measure long, long nimplant/pimplant stripes (150 um long, with 
minimal GATE-size of 1 um) for resistance.
- measure, if the Mask alignment is not so perfect, how this impacts the 
nimplemant/pimplemant resistance.

BTW,
between shared PADs, the internal structure looks like a Resistor (the 
DRAIN-/SOURCE-stripes on one MOSFET-like structure) in parallel to 
Capacitor (the long Poly-Si GATE stripe of another MOSFET-like 
structure).

Regarding your concern, we like to measure with a 4-pin needle probe. 
So, usually we stimulate two PADs with current / voltage and measure on 
both others current / voltage.
My expectation is, that there are no trigger for latch-up or other 
parasitic effects.
And, currently, we can not simulate the structures as we are missing the 
first values. After measuring resistance and capacitance, we get the 
values for the BSIM3v3 Spice-Modell and can simulate more productive 
structures.


And yes, I am aware of my duty to document all thoughts around the test 
structures  :-)

Regards,
Hagen.

[0] 
https://www.amazon.de/Prozeßtechnologie-Fertigungsverfahren-Integrierte-Mos-Schaltungen-Mikroelektronik/dp/3540176705

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Am 03.08.2018 13:28 schrieb Staf Verhaegen:
> Hello,
> 
> I had a quick look at the current PearlRiver design(s). I also see
> layout not schematics or netlists. Do you plan to simulatie your
> measurement procedures before actually manufacturing the wafer ?
> 
> Normal design procedure for analog (test) circuits is first do
> schematic capture, simulate the test procedure and then make layout
> according to schema and make it LVS (layout-versus-schematic) clean.
> 
> Specifically for the L500_MOSFET_aligning structure which is indicated
> to also be used for measuring resistance and capacitance.
> To save pins I see a lot of pins are shared. For example I see that
> the middle pin is both connected to NWELL as to PSUB/PWELL which seems
> dangerous to me.
> In general I see that almost all of the pins are in one way connected
> to NWELL or PSUB/PWELL and basically shorted with other pins through
> these wells and also metal1. So I am wondering which resistances you
> actually try to measure here.
> 
> greets,
> Staf.
> 
> 
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