[Libre-silicon-devel] Netlist and LVS for PearlRiver

[David Lanzendörfer]

Hi Hagen
So now after going through your layout and researching the layers it turns out 
we can perfectly map your layout to our process:
https://www.eda.ncsu.edu/wiki/MOSIS_Layers

The only thing which is missing are pwells.

After lots of thinking I just realized that this is the only problem.
Because the active area is way smaller than the nwell/pwell anyway we're not 
in any danger of building junctions outside of the island.

Also: When we run the STI etching after diffusion any offset in alignment 
won't be a problem because of the spacing between the active area and the 
outer edge of the nwell/pwell.
So we can just expose the pwell and nwell mask for the STI isolation etch.

I've started to add pwells, please have a look at my pull request:
https://github.com/chipforge/PearlRiver/pull/2

Cheers
	David

> I did not look carefully enough and thought all metal1 was shorted between
> center ground pin and the other pins. I know principle of 4-point
> measurement also called force/sense. I have problem figuring out how it is
> applicable to this design. Could you give example for one of the structures
> which pads are used for force and which for sense ? You may not be able to
> simulate structure exactly but you can use some assumed values to see if
> measurement procedure will actually work. Best to include all (parasitic)
> junctions in such simulation. Speaking from experience they often can cause
> problems when sharing pins when they are unwanted biased in forward.
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