[Libre-silicon-devel] Status update
david.lanzendoerfer at o2s.ch
Thu Jul 5 17:38:52 CEST 2018
Following status changes which are partially significant occurred, in a
a) I've now passed the safety examination and should get my RFID access card
to the clean room in a week or so.
>From that point on, the only thing keeping us from running the tests is the
lack of a finalized test wafer layout.
However, since the mask set costs around 1kUSD we shouldn't rush now, because
rushing causes mistakes, and mistakes cost money.
b) I've now worked myself into the topic of creating a generic DRAM controller
out of lightdram, as Luke has suggested.
Turns out it's a bunch of Python scripts which produce a single mashed
together Verilog module. It's a total mess and ugly as hell.
I think I will just "translate" this Python code into Scala/Chisel so that it
can be used directly as an IP core in our SauMauPing framework.
This will be especially relevant as soon as we switch over to the Yuen Long
series which will be a full feature desktop CPU, which mins we will have DIMM/
SODIMM slots soldered to a DDR3/DDR4 bus, connected to the CPU.
So it's already good if we have a nicely parameterizable version of a DDR3/
DDR4 controller inside Chisel.
@Manili: Wanna help with porting the lightram code from Python to Chisel?
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