[Libre-silicon-devel] Status update
david.lanzendoerfer at o2s.ch
Sat Jul 7 12:06:59 CEST 2018
> The thing with this auto generated code is that it meshes everything into
> > verilog module.
> > While Chisel produces nice hierarchical blocks, which makes it way easier
> > to debug and understand.
> > Additionally it basically assumes that "you want" to do an SoC so it
> > kindof
> > doesn't allow for easy extraction of the IP core...
> > Additionally would we get stuck with an IP core with hard coded bus width
> > and so on.
> > Parameters are much nice, wouldn't you say?
> why on earth didn't they put parameters into the python code?? oink??
Exactly. Rocket-Chip generates you a test-bench right along with the core...
> > About the silicon verification: We have to do this anyway, because we
> > develop a new process here. And a iVerilog test bench seems good enough
> > for me to start with.
> cocotb automatically generates and then wraps the iverilog test bench
> and gives a python interface which can be interacted with by the
> python cocotb application.
> i just do not understand why the hell people have been developing
> test benches in verilog. it's basically stone-age technology.
I guess that's Sebastian at it's best once again.
The stuff has been heavily influenced by M-Labs, which mainly means that guy.
And from experience I know that his attitude it "everyone is stupid except
me", so it makes perfectly sense that the stuff he produces is in the fashion
of "I know better than the customer, what the customer needs".
Now take a long good look at the output of this big stack of python files and
their output and start to understand why I'm against getting him into the team
-------------- next part --------------
A non-text attachment was scrubbed...
Size: 195 bytes
Desc: This is a digitally signed message part.
More information about the Libre-silicon-devel