[Libre-silicon-devel] Reminder - next Mumble Session on July 8, 2018 21.00 HKT
david.lanzendoerfer at o2s.ch
Mon Jul 9 19:07:14 CEST 2018
> Also did you check Tile-Link/Chip-Link?
Well, here is what I've looked at so far:
* AXI is backed by a lot of patents backed by US companies.
I've picked out two of the many many patents out there.
* Wishbone from OpenCores – Free and open bus architecture
(formerly from Silicore)
* CoreConnect bus technology from IBM, used in IBM's embedded Power
Architecture products, but also in many other SoC-like systems with the
Xilinx MicroBlaze or similar cores.
Which means it's even more evil than AXI
* IPBus by IDT (Patents ole!)
* Avalon – proprietary bus system by Altera for use in their Nios II SoCs
* Open Core Protocol (OCP) from Accellera
* HyperTransport (HT) from AMD (though this is an off-chip interface,
not on chip bus)
* QuickPath Interconnect (QPI) by Intel (though this is an off-chip
interface, not on chip bus)
* virtual share from PICC - free and open source
However, a Google search didn't spit out useful information.
Apparently it's not so popular
* Tile-Link/Chip-Link  doesn't seem to have been patented yet and seems
to come from universities and the like.
Apparently SiFive have been thinking the same thing we've been thinking.
Candidates now are:
* Tile Link
I'm open for suggestions where we should go from here.
I'd say we should rather use TileLink, because there is already support for it
We can just throw out AXI4 and have no potential patent issues anymore
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