[Libre-silicon-devel] Reminder - next Mumble Session on July 8, 2018 21.00 HKT

Hagen SANKOWSKI hsank at posteo.de
Tue Jul 10 19:50:43 CEST 2018


On 07/10/2018 06:38 PM, Mohammad Amin Nili wrote:
> I tried to search google to find some proper and accurate comparison of AMBA (specially AXI4) and Wishbone (or even other bus protocols) from every aspects (e.g. license, specs, features, throughput etc.). All papers are very old (outdated) or not very useful.
> Anybody could help me?

Well, we have to compile this comparison. Let's start this way -
collecting first the aspect we like to compare and than getting the
I can help somehow while having experiences with a couple of such
System-on-Chip busses; but I do have limited resource collecting all

AMBA is a bundle of different busses.

Mostly known is APB (AMBA Peripherial Bus) for relaxed bandwidth (two
cycles for one data transfer IMHO). Defined someone in the 90ies.

Next, on same Age is AHB (AMBA High Performance Bus) for better
bandwidth (one clock cycle per data transfer) defined for the first
available ARM cores.

AMBA AHB is comparable with Wishbon, IMHO.
Both do have a handshake mechanism, so every data transfer has to be
acknowledged from the receiver cycle by cycle.

Most attention in the current days the AMBA AXI bus gets while promoted
by ARM and Xilinx (as an FPGA vendor).
This AXI does not have the handshake mechanism anymore, so data can be
blown out without waiting the acknowledge from slave, and can be cached
sometimes on longer bus lines without timeouts.
For that, the bus is splitted into three sub-busses, one for writing,
one for reading, and one for control.

For Specs, you have to be registered account on ARM.


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