[Libre-silicon-devel] Reminder - next Mumble Session on July 8, 2018 21.00 HKT
david.lanzendoerfer at o2s.ch
Thu Jul 12 16:36:36 CEST 2018
The advantage about rocket-chip is: It already provides an interface called
TileLink which is free of potentially nasty legal surprises and it can be
easily customized using Chisel3.
Also there are already IP cores in Chisel3 (like UART and SPI) available which
can be easily hooked up to the TileLink interface.
It's pretty straight forward actually.
I'll be gladly using Cliffords yosys for synthesizing the output into a
netlist afterwards though :-)
On Thursday, 12 July 2018 10:26:48 PM HKT R. Timothy Edwards wrote:
> Have you considered just asking Clifford for a wishbone implementation
> in the PicoRV32 code?
> Compared to the amount of work to write and debug the PicoRV32 core, the
> AXI bus adapter is a trivial add-on. The PicoRV32 is open-source and
> Clifford is a fantastic open-source developer. I expect he would be
> able to toss a wishbone bus adapter into the PicoRV32 code faster than
> you could get anyone else to do it, or do it yourselves.
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