[Libre-silicon-devel] Reminder - next Mumble Session on July 8, 2018 21.00 HKT

Tim Edwards tim at opencircuitdesign.com
Thu Jul 12 18:05:03 CEST 2018

Hello David,

> The advantage about rocket-chip is: It already provides an interface called
> TileLink which is free of potentially nasty legal surprises and it can be
> easily customized using Chisel3.
> Also there are already IP cores in Chisel3 (like UART and SPI) available which
> can be easily hooked up to the TileLink interface.
> It's pretty straight forward actually.
> I'll be gladly using Cliffords yosys for synthesizing the output into a
> netlist afterwards though :-)

You seem set on the rocket-chip, which is of course your decision to make.

However, just to set the record straight:

(1) The AXI-lite bus adapter is used in a simple wrapper around the
     picorv32, which itself does not define a bus protocol.  To make
     use of it, you would just synthesize "picorv32_axi" instead of

(2) There is an additional wrapper in the picorv32 source for wishbone,
     for which you would simply synthesize "picorv32_wb" instead of
     "picorv32".  It's all already there (Clifford had to remind me of
     this because I had forgotten that there was a wishbone-compatible
     wrapper in the verilog source).

So just to be sure that you are not misrepresenting Clifford's work,
the statement "Because PicoRV32 is using the axi bus as well, we can't
use this core for our MCU/SoC either" is simply false.


| R. Timothy Edwards (Tim)       | email: tim at opencircuitdesign.com    |
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