[Libre-silicon-devel] Reminder - next Mumble Session on July 8, 2018 21.00 HKT
david.lanzendoerfer at o2s.ch
Thu Jul 12 19:44:27 CEST 2018
Oha. Didn't wanna put the PicoRV32 a bad light or so.
And thanks for the info! Didn't know that PicoRV32 had a native wishbone
Clifford told me a while ago that the chips wouldn't be supposed to be taped
out, and that he specifically made it for FPGA use only.
He was actually kindof annoyed that everyone seems to ignore his warnings
about the core not being suitable for silicon implementation.
So I figured it's maybe anyway a better idea to look out for alternatives.
What I really liked about rocket-chip is the nice abstraction of auto code
generation and modularity.
I mean, I can change it for instance from a 32 bit to a 64 bit architecture
with a few simple lines of code and the periphery stays connected.
And I was thinking it would be a good exercise to try producing a simple MCU
with rocket-chip and afterwards upgrading it to a full multicore SoC with DRAM
port in a further tape out.
That's just how I see it and I'm happy to be taught differently :-)
On Friday, 13 July 2018 12:05:03 AM HKT Tim Edwards wrote:
> You seem set on the rocket-chip, which is of course your decision to make.
> However, just to set the record straight:
> (1) The AXI-lite bus adapter is used in a simple wrapper around the
> picorv32, which itself does not define a bus protocol. To make
> use of it, you would just synthesize "picorv32_axi" instead of
> (2) There is an additional wrapper in the picorv32 source for wishbone,
> for which you would simply synthesize "picorv32_wb" instead of
> "picorv32". It's all already there (Clifford had to remind me of
> this because I had forgotten that there was a wishbone-compatible
> wrapper in the verilog source).
> So just to be sure that you are not misrepresenting Clifford's work,
> the statement "Because PicoRV32 is using the axi bus as well, we can't
> use this core for our MCU/SoC either" is simply false.
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