[Libre-silicon-devel] Pad cells on test wafer

Hagen SANKOWSKI hsank at posteo.de
Sat Jul 21 17:42:31 CEST 2018

Hello David!

On 07/21/2018 04:05 PM, David Lanzendörfer wrote:

> Have you already an idea on how the design of our pad cells will look like?
Yes, I do have a glue..

> How many cascaded drivers stages will the cells contain?

This I like to calculate later, when we know more about our transistor
capabilities - and can estimate W / l for dedicated precise
amplification factor. That's why different transistor structures on our
test wafer are in urgent need.

> How many ESD rings will we provide in the padframe/cells?

At least two, one with GND (connected to p-Substrate) and one with VDD
IO Supply (connected to n-well).

> When I remember right we decided on an active driving capability of 10mA per 
> cell as well as an open-collector option. At least my notes here say this :-)

Yes, this is the target I am working on. I like to check in more stuff
soon :-)


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