[Libre-silicon-devel] Pad cells on test wafer

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat Jul 21 17:45:35 CEST 2018


For anything to do with muxing ie general purpose pu/ pd plus pp/od plus
10/20/30/40mA all as options all needed along with speed filters. Level
shifting builtin also really needed. Same pins get used for i2c spi sdmmc
rgb/ttl some of those are 9600 baud some as high as 125mhz esp RGMII.

Level shifting needed because core IO voltage may be 0.7 on 22nm or 1.1 1.2
on 45nm or 1.8v on 180nm and IOpad anywhere from 1.2-1.8v on mobile systems
right the way to 1.8-3.3v for 180nm.  Typically level shifting is in those
2 ranges, v rare to see 1.2v all way to 3.3v


On Saturday, July 21, 2018, David Lanzendörfer <david.lanzendoerfer at o2s.ch>
wrote:

> Hello Hagen
> Have you already an idea on how the design of our pad cells will look like?
> How many cascaded drivers stages will the cells contain?
> How many ESD rings will we provide in the padframe/cells?
> When I remember right we decided on an active driving capability of 10mA
> per
> cell as well as an open-collector option. At least my notes here say this
> :-)
>
> Cheers
>         David



-- 
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://list.libresilicon.com/pipermail/libre-silicon-devel/attachments/20180721/997eae62/attachment.html>


More information about the Libre-silicon-devel mailing list