[Libre-silicon-devel] Pad cells on test wafer

Hagen SANKOWSKI hsank at posteo.de
Sat Jul 21 20:15:04 CEST 2018


Hello.

On 07/21/2018 07:38 PM, David Lanzendörfer wrote:
> Hi Hagen
> How many metal layers should I plan for the process I'm going to submit soon?

Well, I like to deal with up to three metal layers, not more.

I would guess, that two metal layers are comfortable and reasonable.
Regarding the metal processing I would give metal3 also a chance on
Pearl River.

My assumption is, that the 5um CMP accuracy will bite us in the ass with
metal3 already.

So let's try with 3 metal layers for PearlRiver. If we only get 2 layers
functional, we are still fine - standard cell design mostly still
route-able.

Regards,
Hagen.


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