[Libre-silicon-devel] Pad cells on test wafer

David Lanzendörfer david.lanzendoerfer at o2s.ch
Sat Jul 21 20:54:39 CEST 2018


Hi

> Well, I like to deal with up to three metal layers, not more.
Okey!

> I would guess, that two metal layers are comfortable and reasonable.
> Regarding the metal processing I would give metal3 also a chance on
> Pearl River.
Okey!

> My assumption is, that the 5um CMP accuracy will bite us in the ass with
> metal3 already.
For now, because we use Aluminum interconnect, we don't have to use CMP.
And the CMP at RCL Semi in Tai Po will have not only copper interconnect 
capabilities but a CMP machine better equipped to adequately planarize the 
oxide. 
 
> So let's try with 3 metal layers for PearlRiver. If we only get 2 layers
> functional, we are still fine - standard cell design mostly still
> route-able.
I expect no problems with the 3 metal layers, because the Aluminum can easily 
be etched with the Aluminum etcher.

Cheers
	David
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