[Libre-silicon-devel] Pad cells on test wafer
david.lanzendoerfer at o2s.ch
Sat Jul 21 19:38:01 CEST 2018
How many metal layers should I plan for the process I'm going to submit soon?
BTW: Yesterday I've written the last exam for the chemical safety certificate.
I also submitted my passport photo, so I should get my access card to the lab
within the next few days.
On Sunday, 22 July 2018 12:02:58 AM HKT Hagen SANKOWSKI wrote:
> Hello Luke.
> On 07/21/2018 05:47 PM, Luke Kenneth Casson Leighton wrote:
> > Yes, this is the target I am working on. I like to check in more stuff
> > soon
> > 10mA wont drive sdmmc full speed, or other hi speed 125mhz interfaces
> You are right. We currently working on our Test Wafer - this becomes our
> first free silicon at all. If you like to play with the Magic Tool, you
> can already check some test structures here:
> inside the directories of Library/magic and Layout/magic.
> Feedback welcome!
> We have to characterize all stuff on silicon like resistance /
> capacitance on different layers first, than put the values back to the
> Spice model before we can calculate accurate transistor parameters for
> cells and pads.
> Your wish with multiplexed IO cells is still on the to-do-list.
> And the roughly calculated 10mA driving output cell is for impressing /
> attracting more people. They like blinking LEDs - et voilà we do so
> with on output on the test chip.
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