[Libre-silicon-devel] Pad cells on test wafer

Hagen SANKOWSKI hsank at posteo.de
Sat Jul 21 21:01:28 CEST 2018

On 07/21/2018 08:54 PM, David Lanzendörfer wrote:

>> So let's try with 3 metal layers for PearlRiver. If we only get 2 layers
>> functional, we are still fine - standard cell design mostly still
>> route-able.
> I expect no problems with the 3 metal layers, because the Aluminum can easily 
> be etched with the Aluminum etcher.

Okay, the PearlRiver Test Structures are using up to three metals. Let's
have a look at the results.


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