[Libre-silicon-devel] Reminder - next Mumble Session on July 29, 2018 21.00 HKT
david.lanzendoerfer at o2s.ch
Sun Jul 29 17:42:49 CEST 2018
These are the conclusions from this weeks meeting:
* We decided that blinking circuits are too complex to successfully build on
the Pearl River revision 1 because we would need too many target values and
too complex parts which we can only design after we've got the basic values
from Pearl River 1.
* We've found out that MOSIS lacks ULSI features like a FOX/STI layer as well
as a silicideblock layer, which means we will have to modify Hagens layouts as
soon as I've pushed the Magic layout editor support for LibreSilicon.
So the result of this weeks session has been that we decided to tackle
following tasks until next week:
* Hagen will work on the basic passive circuits required to provide analog
property values of the test wafer
* I (David) will work on the support for LibreSilicon 1um within Tims magic
* Further development on QtFlow (https://github.com/libresilicon/qtflow) is
put on ice because we simply lack man power. Please step forward if you have
On Saturday, 28 July 2018 2:14:45 PM HKT Hagen SANKOWSKI wrote:
> Hello List!
> Just a small reminder for our next Mumble Sessions on this Sunday, July
> 29 at 21.00 Hong Kong Time.
> Please join us as usual at our Mumble Server with IP 126.96.36.199 at
> Port 64738, the Channel is IC.
> On the agenda are (at least) this topics
> - current status
> - test wafer status
> - other stuff around libre silicon
> Happy to hear from you!
> Libre-silicon-devel mailing list
> Libre-silicon-devel at list.libresilicon.com
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