[Libre-silicon-devel] Status update: Silicide
hsank at posteo.de
Fri Apr 26 14:48:54 CEST 2019
On 4/26/19 2:43 PM, David Lanzendörfer wrote:
> Hi everyone
> So this week was pretty productive.
> It turns out, that RCA-1 at room temperature removes all the unreacted
> material perfectly within 20 minutes.
> No more halo this time, anywhere and no more unwanted conductive residue.
> However: The polysilicon expands also laterally when reacted with titanium,
> which leads to a short circuit with the junctions.
> In order to prevent it, we've prepared a second sample wafer, where we will
> deposit around 20 nm of silicon nitride and form the spacers using a dry
Awesome! Thanks for your great work!
> For people not owning a dry etcher (wet-etching-only folks) an additional mask
> will be required unfortunately, in order to cover the poly silicon and silicon
> first with a thin LTO layer and then opening the LTO up only above the poly
> and the to-be-reacted junction areas.
> Unfortunately, next week there is a public holiday (1st May) and Thursday and
> Friday the stepper aligner is offline, so the opening holes and interconnect
> tests with switching report can only be done, Monday in two weeks... :-/
We already got so far. Keep going!
I'm very curios to get more informations from the clean room.
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