[Libre-silicon-devel] [Librecores Discussion] IEEE754 FPU in nmigen
rudi at asics.ws
Sun Feb 17 09:21:44 CET 2019
On Sun, 2019-02-17 at 08:00 +0000, Luke Kenneth Casson Leighton wrote:
> if anyone was ever in doubt about using an OO-based programming
> language for HDL:
> * aleksander and i took a couple of days to work on converting jon
> dawson's excellent 32-bit adder.v to nmigen
> * i took another day to separate out some base classes
> * around 90 minutes to then have the divider.v converted (by doing
> diffs on adder.v and divider.v and using that to identify where to
> modify a copy of add.py to turn it into divide.py)
> * it's taken under an hour to modify the python-based Floating-point
> base class to support 64-bit
> * with the base class in place it then took *under 10 minutes* to
> modify the corresponding divider.py to support 64-bit as well
> so what was originally 300 lines of verilog (adder.v) was duplicated
> for double-precision: the use of python classes has therefore cut the
> amount of code to be maintained in *half*, straight away, and there
> are further reductions of at least 20 to 30% by separating out common
> *parameterised* functionality into the base classes.
> additional savings could be had if there wasn't so much white space
> and additional comments, however that would leave the code sterile
> completely impossible to maintain.
> nmigen rocks!
Curious: What is the cycle time of the generated code versus
native verilog code ?
Rudolf Usselmann, ASICS World Services, LTD, www.asics.ws
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