[Libre-silicon-devel] ADC for Northpoint

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Feb 26 18:03:50 CET 2019


On Tuesday, February 26, 2019, Ludwig Jaffe <ludwig.jaffe at gmail.com> wrote:

> Hi David,
> what memory tech can we do?
> DDR?
>
>
Getting hold even of DDR3 RAM ICs is troublesome.  LPDDR3 is ok (and
pricing ok), DDR3x16 is ok (for now), DDR3x8 is *NOT* ok, I know of only
one company that can do 4gbit ICs here in Taiwan and I had to buy 5000 @
USD 3.30 each for them to actually bother.

DDR2 would almost certainly be a total waste of time.

SDRAM doesn't do DDR, it is basically the ISA bus aka Flexbus aka IDE aka
AT/XT aka PCMCIA aka CompactFlash aka MCU 8800 Bus aka NAND Flash bus they
are hilariously all the same signalling.

Even implementing DDR3 is risky as it is going out of fashion since apple
and intel products started dominating foundry supply with massive DDR4
orders, no spare capacity to make DDR3, which was why China opened up some
DRAM foundries last year (and probably why the bunfight between US and
China, accusations of theft etc blah blah zzzzz).

Seriously considered talking to fabless companies, combine OpenRAM with 4
to 8 HyperRAM interfaces.  Would not need the mad timings and dynamic
impedance matching. HyperRAM is diff pair on the clock line only when put
into DDR mode. Only goes up to 150mhz clock rate so 300mbytes/sec in DDR
mode. Bit like SDMMC. Also DDR mode only doable in 1.8v.

HyperRAM another one where diff pair Rx and Tx needed although Tx is just a
NOT gate on one line. Rx bit more complex, need comparator to check which
CLK line is hi which is lo.

L.



-- 
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