[Libre-silicon-devel] KiCAD VLSI design

Hagen SANKOWSKI hsank at posteo.de
Thu Jan 24 08:06:32 CET 2019

Hello Tatzelbrumm!

On 1/23/19 10:13 PM, Christoph Maier wrote:
> On Wed, Jan 23, 2019 at 10:05 PM Hagen SANKOWSKI <hsank at posteo.de> wrote:
>> Last May we did our 1st LibreSilicon Hackathon to evaluate all the tools
>> and formats, which could be interesting for us.
>> Well, I like to re-post the Outcome here again
>>         https://hackmd.c3d2.de/libresilicon
>> The site is in German and should be almost complete.
> As I have some time to think, I wonder:
> Has any of you done an actual analog IC design, comprising
> * (parametric) cell definition
> * schematic capture
> * schematic simulation (corners? Monte Carlo??)
> * layout (schematic driven? manual??)
> * Layout DRC
> * LvS
> * layout parasitic extraction
> * post layout simulation
> * streamout (to CIF? to GDS??)
> with any of these tool chains?

You are the Pioneer on the white territory where no one was gone before.
As chancellor Merkel would say: You´re are entering "Neuland".

On the gEDA tools suite (should be also on the Lepton EDA fork) as well
as KiCAD are tools for Schemetic entry, export to Spice3f and simulate
with ngspice. Here the Monte Carlo Simulation is involved.

On Magic there is a tool which does the task from Layout to Spice3f
export. Here should be the Layout Parasitic extraction. And with ngspice
again Post Layout Simulation.

BTW, should be possible to go from Schematic (in Ascii) to Magic (in
Ascii).. be script or hand.

Magic has the streamout to CIF and GDS2 - we already did the PearlRiver
Testwaver this way.

For the whole flow, I guess a lot of tools are missing.
Please find your way, ask on the list, hopefully someone here can give
you a helping hand or provide a tool.
Also to collect all informations, you're figuring out on your way
through the analog design flow, somewhere on a Blog, Wiki, or even paper
on the list would be great.

> In the meantime, I'm trying to get academic local access to Cadence,
> so that I can separate the task of designing proof-of-concept analog
> circuits from developing and maturing a tool chain.

Every Journey starts with a small Step.


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