[Libre-silicon-devel] Update: RCL cross verification
leviathan at libresilicon.com
Tue Jul 9 14:39:04 CEST 2019
So I've had a mail exchange and we can go through our recent status together
with the engineers at RCL, as soon as we're done cleaning up everything.
a) We've gotta rework PearlRiver, so that it's in accordance with the new
design rules which arose from the R&D.
Mainly: Contact holes should all have the same size because the dry etching
time is varying with the area of the contact hole.
So the yield goes into the basement when the vias/contacts in the oxide all
have different dimensions.
b) Also I'm right now cleaning up the documentation for the process so that it
reflects what I've actually done the past year in the lab.
c) After we're done with it, we'll do some legal stuff and can most likely
make a test run.
I don't think the engineers checking our process will tell us to fuck off,
since we're not just a bunch of bat shit crazy dilettantes but actually know
what we're doing and I believe this will be clearly reflected in the artwork
(updated PearlRiver GDS files) and updated documentation.
So we're on a good way.
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